Higher performance, lower cost, increased miniaturization of components, and greater packaging density of semiconductor devices are ongoing goals of the electronics industry. Two significant classifications of semiconductor devices are logic and memory. Logic devices are used, in combinations conventionally termed microprocessors, primarily to process information. Memory devices, on the other hand, are used for information storage. Conventionally, while these two device types are found in virtually all electronic systems, such as computers and the like, they have been manufactured on separate integrated circuits and connected only at the card or board level. This has been due to differences in manufacturing processes, cost considerations, economies of scale, and other difficulties in fabricating the different device structures on a common substrate.
Trends in the semiconductor industry have led to making it more desirable and feasible to blend memory and logic on the same integrated circuit. Typically, in such structures a memory cell and a logic device are formed side-by-side in a single plane on a common substrate. Such integrated circuits are described in detail in, for example, U.S. Pat. No. 5,719,079 to Yoo et al. which is entitled Method of Making a Semiconductor Device Having High Density 4T SRAM in Logic with Salicide Process, U.S. Pat. No. 6,353,269 to Huang which is entitled Method for Making Cost-Effective Embedded DRAM Structures Compatible with Logic Circuit processing, U.S. Pat. No. 6,573,604 to Kajita which is entitled Semiconductor Device Carrying Memory and Logic Circuit on a Chip and Method of Manufacturing the Same, and U.S. Patent Application Publication No. 2008/0157162 to Doyle which is entitled Method of Combining Floating Body Cell and Logic Transistors, the disclosures of each of which document is incorporated herein in its entirety by this reference.
There are several drawbacks to these integrated circuits with memory and logic positioned side-by-side on the same substrate. For example, state-of-the-art multi-core microprocessors may have 4 or 16 processors on a single substrate. Each processor requires that a significant portion of the area, or “real estate” on the active surface of the substrate be occupied by associated memory, consequently requiring a larger than desirable semiconductor substrate or, stated another way, an undesirably low number of processors on a given size substrate. Additionally, there may be structural limitations for arranging the various processors on the substrate so that each processor has adequate access to memory without unnecessarily consuming real estate or utilizing undesirable signal lengths. Furthermore, while SRAM is conventionally the memory integrated with logic devices, SRAM structure does not provide good circuit density due to the number of required components per cell. The SRAM fabrication process is compatible with that of logic devices; however, the overall process flow is inefficient.
In addition, conventional fabrication techniques which might otherwise be used to combine memory with logic are impractical, due to the high temperatures utilized in forming memory on a substrate already comprising logic and metallization associated therewith.
Accordingly, there are needs for processes in which memories and logic can be formed on a common substrate while minimizing the amount of active area on the substrate needed and maintaining efficiency of and accessibility to memory by the logic.